The present invention relates to a burn-in technique of a semiconductor device. The present invention also relates to, for example, in a semiconductor device like a MCP (Multi Chip Package) having two semiconductor chips thereof formed as a SRAM, a flash memory and the like, a technique effectively applied to a test system suitable for a contact check method used between each needle and each terminal of the semiconductor chips at burn-in performed under the state of a semiconductor wafer.
As a technique that the present inventors have studied, a burn-in technique of the semiconductor device is considered as follows. That is, for example, the burn-in technique of a MCP forming a SRAM and a flash memory has the steps of forming respective semiconductor chips of the SRAM and the flash memory to a substrate, connecting electrically the semiconductor chips and the substrate by a wire bonding or the like, molding the semiconductor chips and the substrate with a resin to assemble a packaging structure, and then testing the packaging structure, wherein a temperature and an electrical stress which exceed a rating are applied to perform the burn-in technique. Because this burn-in performs a screening to eliminate some MCPs that may become bad (i.e., defective) in the future, only good MCPs are shipped as products.
Now, as a result of consideration of the above-mentioned burn-in technique by inventors of the present invention, certain findings became apparent. For example, in a method of performing the burn-in after assembly of the MCPS, as described above, yield of each semiconductor chip of the SRAM and the flash memory largely affects that of the assembled MCPs, so that there is status not being capable of expectedly improving the yield of the MCPs. That is, in case of adopting this method, if either semiconductor chip of the SRAM or the flash memory becomes bad, MCPs assembled by using these bad semiconductor chips also become bad in quality and it seems thereby that the yield of the assembled products decreases.
Therefore, the present inventors have had an idea of a method of performing the burn-in at a stage of a semiconductor wafer, and assembling the MCPs after bad semiconductor chips are redundantly relieved or are eliminated, in order to improve the yield of each semiconductor chip of the SRAM and the flash memory. At this time, it is necessary to perform electric contact check between each of the needles connected to a test apparatus and each of the terminals of the semiconductor chips. Therefore, for example, similarly to the assembled product, a method can be used in which a voltage is applied between each of the needles and each of the terminals to be electrically conducted to the needles, and an electric connection/non-connection is judged by detecting electric current flowing therebetween.
However, it is difficult to make this current-detecting method of applying the voltage corresponding to a multi-pin scheme depending on the number of terminals in accordance with high performance and large capacity of the recent semiconductor devices. That is, as the number of terminals of the semiconductor chips increases, needles, ammeters and the like corresponding to this number of terminals are required and, hence, these increasing numbers become enormous. Therefore, it is difficult to use practically the current-detecting method.
An object of the present invention is to provide a test system of a semiconductor device, wherein, while a method of performing the burn-in at a stage of semiconductor wafer is applied, improvement of the yield of assembling products can be achieved by using a small number of needles and a small number of contact terminals at the burn-in, performing an electric contact check between each needle and each terminal of semiconductor chips, and utilizing good semiconductor chips subjected to the burn-in.
The above-mentioned and other objects and novel characteristics of the present invention will be apparent from description of the present specification and the accompanying drawings.
Regarding the disclosure in this application, a summary of representative inventive aspects thereof will now be described.
That is, a first semiconductor wafer according to the present invention is applied to a semiconductor wafer including a plurality of semiconductor chip areas, each of which has a memory matrix, each of the semiconductor chips having a first terminal which inputs a signal for judging electric connection/non-connection between a needle connected to a test apparatus at burn-in and a terminal provided in each of the semiconductor chips, and a second terminal which outputs a response signal for responding to this input signal.
A second semiconductor wafer according to the present invention is one that each of the semiconductor chips has a plurality of address input terminals for specifying an address of a memory matrix, and a plurality of data input/output terminals for inputting and outputting write data and read data, and a plurality of control signal terminals for controlling write and read operations, and a plurality of test-only signal terminals for judging electric connection/non-connection between a needle connected to a test apparatus at burn-in and a terminal provided in each of the semiconductor chips.
Also a semiconductor chip according to the present invention comprises a memory circuit having a volatile memory matrix, and a test circuit inputting a signal for judging electric connection/non-connection between a needle connected to a test apparatus at burn-in and a terminal of the semiconductor chip and outputting a response signal for responding to this input signal, and judging electric connection/non-connection between a needle connected to the test apparatus at the burn-in and a terminal of the semiconductor chip.
Moreover, the test circuit of the semiconductor chip comprises a test clock terminal for inputting a test clock signal, a first and second test control terminals for inputting a test control signal, a test input/output terminal for inputting and outputting test input/output data, a power terminal supplied with a power supply voltage, and an earth terminal supplied with an earth voltage.
And, said test circuit synchronizes the test control signal being input from the test clock terminal to be controlled in accordance with a combination of the test control signals being input from the first and second test control terminals, and has a shift register for shifting test command data being input from the test input/output terminal and a decoder for decoding data for this shift register, such that operation of a test mode is initiated in accordance with a current status flag and a concurrent status flag being output from the decoder.
Moreover, said test circuit has a counter for counting synchronously the test clock signal being input from the test clock terminal, and uses a count value of the counter as an address signal of the memory circuit at the test mode, and outputs a carry signal of the counter from the test input/output terminal to thereby judge electric connection/non-connection between each needle and each terminal of the semiconductor chip in the test apparatus.
Additionally, said carry signal of the counter is used as write data of the memory circuit. Alternatively, the carry signal of the counter and the read data of the memory circuit are operated by exclusive OR, and output from the test input/output terminal, and are used as a monitor of bad rate during the burn-in.
Also, a manufacturing method of semiconductor devices according to the present invention is applied to the manufacture of semiconductor devices in which semiconductor chips are cut from a semiconductor wafer and a first semiconductor chip and a second semiconductor chip, separated from each other, are formed, the method comprising a step of performing burn-in of the first and second semiconductor chips before the semiconductor chips are cut out from the semiconductor wafer.
Moreover, said step of performing burn-in includes a step of performing a contact check for judging electric connection/non-connection between each needle connected to a test apparatus and each terminal provided in each of the first and second semiconductor chips of the semiconductor wafer.